Browsing by Subject "Interference cancellation"

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Circuits and architectures for the implementation of broadband channelizers
(2017-01-10) Ho, Wei-Gi; Gharpurey, Ranjit; Abraham, Jacob; Orshansky, Michael; Touba, Nur; Pullela, Raja
Broadband spectrum channelizers sub-divide a broadband input spectrum into multiple sub-bands, where each of the sub-bands is down-converted and further processed at baseband. These designs can help to relax baseband design specifications. For example, baseband analog-to-digital converters (ADCs) that process the sub-bands at the channelizer output see only a part of the incident spectrum. The sampling frequency, and potentially the dynamic range of each sub-band ADC can thus be relaxed, compared to the case where a single ADC is used to digitize the full spectrum. Spectrum channelizers can be used for multiple applications. These designs can be used as general-purpose hybrid frequency-and-time domain ADCs. The designs can also be employed for spectrum analysis, as well as for wireless communication applications. In this dissertation, two circuit techniques for the implementation of broadband channelizers are proposed. A frequency-translational feedback-based interference canceler for attenuating large interferers at the output of the front-end low-noise amplifier (LNA) of a channelizer is shown. The design uses harmonic rejection mixers (HRMs) with embedded frequency synthesis capability. While channelizers reduce the bandwidth and potentially the dynamic range of the baseband ADCs, the analog signal paths in the channelizer can be broadband. Consequently the dynamic range required of the analog section of a sub-band path can still be limited by the presence of large signals in other, potentially distant parts of the spectrum. The demonstrated design is useful for relaxing the dynamic range requirement of the analog section that follows the front-end LNA in a channelizer. Reduction of the harmonic response and the frequency synthesizer tuning-range is also achieved in this design. Second, a two-stage HRM is proposed which shares the same bias current between the RF and baseband stages, thus reducing the power consumption. Issues arising from bias-current sharing, such as the 1/f noise of the RF stage and potential degradation of the 2nd harmonic response are identified, and circuit techniques are introduced to mitigate these potential degradation mechanisms.
Linearity analysis of microwave photonic links for analog signal processing
(2022-07-01) Mokhtari Koushyar, Farzad; Bank, Seth Robert; Vishwanath, Sriram; Campbell, Joe C; Wasserman, Daniel M; Nanzer, Jeffrey
Microwave photonics (MWP) provides wideband, programmable, and low-loss platforms for analog signal processing with high power handling and immunity to electromagnetic interference. Recent advancements in integrated photonics have enabled a variety of on-chip functions for signal processing including true-time delays, tunable switches, high-Q resonators, frequency combs, and so on which make MWP a promising solution for ever-increasing demand of high throughput signal processing. However, achieving the desired dynamic range (DR) from MWP links has remained elusive for signal processing applications. The nonlinear sources of MWP links are studied with a focus on integrated MWP for signal processing. The concept of interference induced distortions (IIDs) are introduced which are generated by passive structures in the link. As demonstrated by the presented theory, simulations, and measurement results, IIDs from passive components can dominate the nonlinear distortions of active components in the link by tens of dB. The impact of parasitic interferometric structures which are formed by design, fabrication, and packaging imperfections on IIDs are discussed along with mitigation solutions. The impact of frequency chirp in active devices on IIDs are studied by simulation and measurement results which shows a magnified sensitivity of IIDs to parasitic interferences when chirp increases. On-chip tap combination, however, is a desired interference in many applications which its implementation remains challenging due to instabilities and limited DR originating from IIDs. Incoherent combiners are proposed in the literature based on multiple PDs or wavelengths at the cost of limiting bandwidth, increasing insertion loss, and necessitating a frequency comb. A tapered-pitch array combiner (TPAC) is introduced here to break the trade-offs in the incoherent and off-chip solutions. TPAC is designed based on the rules derived from the theory and simulation presented for modeling IIDs. A SFDR₃ equal to 107.3 dBc.Hz [superscript 2/3] is measured for the fabricated TPAC combing taps of a 6-tap filter using one wavelength and one PD. A modified TPAC is proposed for further IID suppression using optical phase alignment (OPA) of taps where up to than 26.9 dB IMD₃ suppression is measured. Finally, the stability and tunability of OPA approach are discussed followed by suggestions for future research.