Browsing by Subject "Design automation"

Now showing 1 - 7 of 7

A simulation-based analog IC synthesis tool using SBDE optimization algorithm
(2018-05-04) Wang, Yunyi, M.S. in Engineering; Sun, Nan
Although Analog Integrated Circuits (ICs) only account for a small portion of the entire modern System-on-a-Chip (SoC), their design is one of the most challenging work, demanding extensive knowledge and huge effort. In order to shorten the Time-To-Market (TTM), Electronic Design Automation (EDA) tools are essential for assisting designers by reducing laboring work and helping their decision-making. This thesis presents an analog circuit synthesis tool, which sizes circuits to meet design specifications. The tool adopts the simulation-based approach which encapsulates a SPICE simulator, and uses Selection-Based Differential Evolution (SBDE) as the global optimization algorithm. Synthesis speed is boosted by conducting parallel evaluations, and designer’s preparatory effort is reduced by a user-friendly system architecture without compromising accuracy or flexibility. Three circuit testbenches are synthesized successfully in relatively short time, which demonstrates the effectiveness and efficiency of the tool.
Computational automation for efficient design of acoustic metamaterials
(2022-01-26) Wiest, Tyler James; Seepersad, Carolyn; Haberman, Michael R. (Michael Richard), 1977-; Crawford, Richard; Lee, Kevin
Acoustic metamaterials (AMMs) are an exciting technology because they are capable of responding to vibrations in ways that are impossible to achieve with conventional materials. However, realization of AMMs requires engineering design to provide a connection between first-principles research and production of parts that perform as expected. Designing AMMs is a challenging endeavor because evaluating designs is costly and manufacturing metamaterials requires precise techniques with small minimum resolutions. To address these challenges, new computational tools are necessary to aid design. This work proposes three tasks that improve the capabilities of design for AMM while being extensible to other engineering design automation tasks. The first task is to develop a design exploration tool that improves the computational efficiency of identifying sets of high-performing designs in a design space that is sparse and comprises mixed discrete/continuous data. The second task is to develop a process for designers to evaluate manufacturability of difficult-to-manufacture parts and drive co-development of manufacturing methods and AMM. In the final task, a machine learning based method is developed to efficiently model AMM with heterogeneous arrangements of their microstructures such that strict homogenization is infeasible. The outcomes from completing these tasks will provide a significant and novel improvement over existing methods of designing AMMs.
Design and automation techniques for hIgh-performance mixed-signal circuits
(2022-05) Shi, Wei (Ph. D. in electrical and computer engineering); Sun, Nan; Pan, David Z.; Orshansky, Michael; Han, Song; Kulkarni, Jaydeep
In the era of ubiquitous sensing environment, the modern electronic system expands our perception of the outside world. Analog/mixed-signal circuit has played a critical role to bridge the physical and digital worlds. The boom of Internet-of-Things (IoT), bio-sensing, and digital camera calls for versatile high-performance mixed-signal circuits and the corresponding automated design methodology. However, high-performance analog circuits are area or power hungry. Moreover, the design cost is prohibitively expensive. To address these challenges, this dissertation explores solutions from both the design and automation techniques. Analog-to-digital converter (ADC) is an important subset of analog/mixed-signal circuits. Continuous time Delta-Sigma modulator (CTDSM) is a popular design choice for high-speed and high-resolution designs. CTDSMs feature a higher power efficiency than their discrete-time (DT) counterpart. The first work presents a high-speed 4th-order DSM featuring the CT-DT hybridization and an efficient excess-loop-delay (ELD) compensation technique in the charge domain. Compared to prior high-order CTDSMs, the proposed hybrid DSM achieves 4th-order noise shaping with single operational trans-conductance amplifier (OTA). Minimized number of OTAs reduces power and enhances stability. On top of that, an efficient ELD compensation technique is implemented by utilizing the inherent capacitor digital-to-analog converter (CDAC) of SAR. Fabricated in 40 nm CMOS, the prototype ADC achieved a peak Schreier Figure-of-Merits (FoM) of 176.1 dB, marking 4 dB improvement over prior arts. The second project explores the techniques to reduce the area consumption of high-resolution CTDSMs. The performance of existing high-resolution CTDSMs is limited by the feedback DAC. The stringent non-linearity requirement leads to the large area of DAC. To address this limitation, a low-complexity hardware-based 2nd-order dynamic-element-matching (DEM) is proposed. The partial sorter applied to the DEM minimizes the hardware cost. Moreover, feedforward path assisted loop filter adapts the highly-linear integrator design to the low power supply voltage. With these techniques combined, the prototype shows a feasible design pattern to achieve compact-area, high-resolution design at advanced technology nodes. A prototype fabricated in 40 nm CMOS measured 95dB SNDR, occupying only 0.37 mm² area. After the exploration of pushing the ADC performance boundary, this dissertation also demonstrates the automated design methodology. The design cost of high-performance mixed-signal circuit grows exponentially with the technology scaling. Existing analog automation techniques cannot handle practical circuit design constraints (e.g. robustness against variations). The third work presents RobustAnalog, a variation-aware analog circuit optimization via multi-task reinforcement learning (RL) and task-space pruning. RobustAnalog is mainly designed to tackle the process-voltage-temperature (PVT) robustness in the analog design. Correlations between similar variations are modeled and conflicts between distinct variations are mitigated. With task pruning, a small-sized proxy training task set is formed. The pruning reduces the queries to the full task set. Compared with the popular blackbox optimization methods, RobustAnalog significantly reduces the simulation cost. Therefore, RobustAnalog shows the staggering progress towards analog automation techniques that can be applied to real silicon conditions.
A graph grammar scheme for representing and evaluating planar mechanisms
(2010-05) Radhakrishnan, Pradeep, 1984-; Campbell, Matthew I.; SV, Sreenivasan
There are different phases in any design activity, one of them being concept generation. Research in automating the conceptual design process in planar mechanisms is always challenging due to the existence of many different elements and their endless combinations. There may be instances where designers arrive at a concept without considering all the alternatives. Computational synthesis aims to arrive at a design by considering the entire space of valid designs. Different researchers have adopted various methods to automate the design process that includes existence of similar graph grammar approaches. But few methods replicate the way humans’ design. An attempt is being made in the thesis in this direction and as a first step, we focus on representing and evaluating planar mechanisms designed using graph grammars. Graph grammars have been used to represent planar mechanisms but there are disadvantages in the methods currently available. This is due to the lack of information in understanding the details of a mechanism represented by the graph since the graphs do not include information about the type of joints and components such as revolute links, prismatic blocks, gears and cams. In order to overcome drawbacks in the existing methods, a novel representation scheme has been developed. In this method, labels and x, y position information in the nodes are used to represent the different mechanism types. A set of sixteen grammar rules that construct different mechanisms from the basic seed is developed, which implicitly represents a tree of candidate solutions. The scheme is tested to determine its capability in capturing the entire set of feasible planar mechanisms of one degree of freedom including Stephenson and double butterfly linkages. In addition to the representation, another important consideration is the need for an accurate and generalized evaluator for kinematic analysis of mechanisms which, given the lack of information, may not be possible with current design automation schemes. The approach employed for analysis is purely kinematic and hence the instantaneous center of rotation method is employed in this research. The velocities of pivots and links are obtained using the instant center method. Once velocities are determined, the vector polygon approach is used to obtain accelerations and geometrical intersection to determine positions of pivots. The graph grammar based analysis module is implemented in an existing object-oriented grammar framework and the results have found this to be superior to or equivalent to existing commercial packages such as Working Model and SAM for topologies consisting of four-bar loop chain with single degree of freedom.
Lithography variability driven cell characterization and layout optimization for manufacturability
(2011-05) Ban, Yong Chan; Pan, David Z.; Abraham, Jacob; Touba, Nur; Lucas, Kevin; Orshansky, Michael
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed.
Machine learning for analog/mixed-signal IC design : scaling from circuits to systems
(2022-11-27) Liu, Mingjie; Pan, David Z.; Sun, Nan; Kulkarni, Jaydeep P; Jia, Yaoyao; Ren, Haoxing
Analog and mixed-signal integrated circuits are widely used in many emerging applications, and the increasing demand calls for a shorter design cycle and time-to-market. Traditionally the design process is dominated by manual efforts and is very time-consuming, which involves design experts iterating between the circuit sizing and layout implementation steps. Despite attempts to automate the design process for analog circuits, prior works fail to scale from design automation of simple component level circuits to systems of larger size. Furthermore, few works have considered post-layout parasitic effects during circuit sizing, limiting the practical application in designing real chips targeting tape-out fabrication. This dissertation will explore methods to apply machine learning to analog and mixed signal circuit design automation in terms of practicality and scalability. Specifically, this dissertation will study and explore: Graph spectral and machine learning methods to automatically assign layout symmetry constraints from unannotated netlists of large circuit systems such as analog to digital converters (ADCs); Machine learning methods and models (such as convolutional neural networks and graph neural networks) to quantify analog layout quality and layout parasitic estimation without invoking parasitic extraction and circuit simulations; Efficient circuit sizing with Bayesian Optimization and in-the-loop layout generation that guarantees post layout performance, allowing design automation techniques to scale to the system-level design of an ADC. Finally, this work will be backed up by both circuit simulation results and real chip tape-out measurements to demonstrate the effectiveness of applying machine learning to automatically design analog circuits, which scales to analog system designs such as ADCs
Physical design automation of structured high-performance integrated circuits
(2013-12) Ward, Samuel Isaac; Pan, David Z.
During the last forty years, advancements have pushed state-of-the-art placers to impressive performance placing modern multimillion gate designs in under an hour. Wide industry adoption of the analytical framework indicates the quality of these approaches. However, modern designs present significant challenges to address the multi objective requirements for multi GHz designs. As devices continue to scale, wires become more resistive and power constraints significantly dampen performance gains, continued improvement in placement quality is necessary. Additionally, placement has become more challenging with the integration of multi-objective constraints such as routability, timing and reliability. These constraints intensify the challenge of producing quality placement solutions and must be handled carefully. Exasperating the issue, shrinking schedules and budgets are requiring increased automation by blurring the boundary between manual and automated placement. An example of this new hybrid design style is the integration of structured placement constraints within traditional ASIC style circuit structures. Structure aware placement is a significant challenge to modern high performance physical design flows. The goal of this dissertation is to develop enhancements to state-of-the-art placement flows overcoming inadequacies for structured circuits. A key observation is that specific structures exist where modern analytical placement frameworks significantly underperform. Accurately measuring suboptimality of a particular placement solution however is very challenging. As such, this work begins by designing a series of structured placement benchmarks. Generating placement for the benchmarks manually offers the opportunity to accurately quantify placer performance. Then, the latest generation of academic placers is compared to evaluate how the placers performed for these design styles. Results of this work lead to discoveries in three key aspects of modern physical design flows. Datapath placement is the first aspect to be examined. This work narrows the focus to specifically target datapath style circuits that contain high fanout nets. As the datapath benchmarks showed, these high fanout nets misdirect analytical placement flows. To effectively handle these circuit styles, this work proposes a new unified placement flow that simultaneously places random-logic and datapath cells. The flow is built on top of a leading academic force-directed placer and significantly improves the quality of datapath placement while leveraging the speed and flexibility of existing algorithms. Effectively placing these circuits is not enough because in modern high performance designs, datapath circuits are often embedded within a larger ASIC style circuit and thus are unknown. As such, the next aspect of structured placement applies novel data learning techniques to train, predict, and evaluate potential structured circuits. Extracted circuits are mapped to groups that are aligned and simultaneously placed with random logic. The third aspect that can be enhanced with improved structured placement impacts local clock tree synthesis. Performance and power requirements for multi-GHz microprocessors necessitate the use of a grid-based clock network methodology, wherein a global clock grid is overlaid on the entire die area followed by local buffered clock trees. This clock mesh methodology is driven by three key reasons: First, full trees do not offer enough performance for modern microprocessors. Second, clock trees offer significant power savings over full clock meshes. Third, local clock trees reduce the local clock wiring demands compared to full meshes at lower level metal layers. To meet these demands, a shift in latch placement methodology is proposed by using structured placement templates. Placement configurations are identified a priori with significantly lower capacitance and the solutions are developed into placement templates. Results through careful experimentation demonstrate the effectiveness of these approaches and the impact potential for modern high-speed designs.