Browsing by Department "Electrical and Computer Engineering"
Now showing 1 - 10 of 2058
Results Per Page
Item1.1V Supply Vth based CMOS voltage reference and analog multiplier for low power applications(2019-05-09) Li, Xichen; Viswanathan, T.R., doctor of electrical engineeringThe development of low power integrated system is expected to lead to the expansion of next-generation power-efficient applications. A voltage-reference is widely used in integrated circuits to generate an on-chip reference voltage. The generated voltage-reference is used for building blocks like analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Because voltage reference is an important building block of analog design, development of low power voltage reference circuits requires special attention. This thesis presents a new circuit topology to produce a single ended output proportional to absolute temperature (PTAT) voltage for building a voltage-reference circuit. PTAT voltage is generated by two diode-connected MOSFETs in the subthreshold region. Complementary to absolute temperature (CTAT) voltage is realized, which has negative temperature coefficient (TC), by the gate-source voltage of a MOSFET in the subthreshold region. This design has low power dissipation and simple circuit. With a supply voltage of 1.1V, this circuit designed and fabricated in 0.18μm CMOS technology dissipates 2.2μW. Similar circuit topology can also be used to design a nano-ampere one quadrant analog multiplier with high tolerance to process and temperature variations ItemA 12-bit, 10 Msps two stage SAR-based pipeline ADC(2012-12) Gandara, Miguel Francisco; Sun, Nan; Gharpurey, RanjitThe market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is presented that attempts to mitigate some of the sampling rate limitations of a SAR while maintaining its power and resolution advantages. Special techniques are used to reduce the overall sampling capacitance required in both SAR stages and to increase the linearity of the multiplying digital to analog converter (MDAC) output. The SAR sampling network, control logic, and MDAC blocks are completely implemented. Ideal components were used for the clocking, comparators, and switches. At the end of this design, a figure of merit of 51 fJ/conversion-step was achieved. Item2D and 3D multiphase active contours without edges based algorithms for simultaneous segmentation of retinal layers from OCT images(2013-05) Klotz, Andrew Criston; Rylander, H. Grady (Henry Grady), 1948-Glaucoma is a common disease that is difficult to diagnosis early using only visual field tests. Current research indicates that determination of retinal nerve fiber layer thickness (RNFLT) can serve as an early indicator of glaucoma . RNFLT is measured by segmenting non-invasive optical coherence tomography images. However, high speckle noise and presence of artifacts in the images cause traditional layer detection and segmentation methods to fail. Multiphase active contours segmentation methods utilize region intensity and shape terms to produce multiple continuous boundaries simultaneously in noisy environments. A 2D and 3D multiphase active contours based algorithm was created to segment synthetic and real human retina OCT images. The 2D multiphase algorithm segmented eight simultaneous layers with a 3.14% mean A-scan error rate per layer. The 3D approach performed qualitatively accurate segmentation of a 20 image stack simultaneously. In an artificial, high-noise image stack the incorporation of more pixels per layer allowed improved segmentation using the 3D algorithm over the 2D. These results indicate that 2D and 3D multiphase active contours algorithms can be used to accurately segment retina layers. With further development to reduce computation time and automate initialization, these algorithms could be used to provide close to real-time clinical retinal image segmentation. Item2D memristor reliability and modeling for neuromorphic computing(2023-03-31) Huang, Yifu; Lee, Jack Chung-Yeung; Akinwande, Deji; Banerjee, Sanjay; Dodabalapur, Ananth; Shi, LiTwo-dimensional (2D) materials have been reported to exhibit non-volatile resistive switching (NVRS) phenomenon and applied on memristors or resistive random-access memory (RRAM) devices over the past few decades. Recent research further demonstrates the potential for 2D RRAM devices to be implemented in neuromorphic applications. However, reliability is a major challenge for practical application and industrialization. This dissertation presents the improvement of reliability in 2D material-based memristors and in-depth research in electrical characteristics, failure mechanisms, modeling, and neuromorphic applications. Chapter 2 discusses the reliability improvement of 2D monolayer MoS₂-based memristors by electron irradiation treatment. Sulfur vacancies, the density of which is modified by irradiation dosage, are revealed to be significant in the improvement of yield and endurance. Finite element analysis and Monte Carlo modeling are applied to help understand the role of sulfur vacancies in resistive switching and reliability improvement. In Chapter 3, further optimizations in reliability have been done by introducing sulfurization method in the preparation of MoS₂ films and the fine tune of metal deposition, extending the defect engineering from monolayer to multilayer MoS₂. Intriguing convergence of resistive switching metrics from the statistical measurements is highlighted along with the largely improved endurance performance. An effective switching layer model has been proposed to illustrate the underlying physics of endurance improvement and switching metrics convergence. In Chapter 4, a Monte Carlo modeling tool, which helps visualize the physical process and provides additional insight into the effective switching layer model, is discussed in detail. Transmission electron microscope (TEM) measurements provides experimental support to the model. In Chapter 5, pulse measurements of 2D ReSe₂-based memristors are discussed, demonstrating long-term potentiation and depression (LTP and LTD) behaviors in long-term plasticity programming. A Verilog-A model is proposed based on the multiple-step resistive switching behavior. Further, an artificial neural network (ANN) is trained based on the LTP/LTD parameters from experiments, showing the potential application of 2D memristors. In Chapter 6, the application of the constructed ANN model is discussed by investigating the temperature effect in TaOₓ-based memristors. The simulation results provide additional insights for the designs of potential hardware-based neuromorphic computing applications. Item3D image processing and FPGA implementation for optical coherence tomography(2013-08) Carroll, Sylvia D; Milner, Thomas E.This thesis discusses certain aspects of the noninvasive imaging technique known as optical coherence tomography (OCT). Topics include three-dimensional image rendering as well as application of the Fast Fourier Transform to reconstruct the axial scan as a function of depth. Implementations use LabVIEW system design software and a Xilinx Spartan-6 field-programmable gate array (FPGA). The inherent parallel-processing capability of an FPGA opens the possibility of designing a "super-sensor" which entails simultaneous capturing of image and sensor data, giving medical practitioners more data for potentially improved diagnosis. FPGA-based processing would benefit many methods of characterizing biological samples; OCT and photonic crystal microarray biosensors are discussed. Item3D system-circuit-device design methodologies for advanced CMOS(2021-05-03) Mathur, Rahul; Kulkarni, Jaydeep P.; John, Lizy; Dodabalapur, Ananth; Banerjee, Sanjay; Yeric, Greg; Sinha, SaurabhThe emergence of 5G, automotive, and AI-based applications are creating new capabilities and a huge amount of data that is driving the need for a broad expansion in energy-efficient compute capacities. At the same time, the typical gains in Power, Performance, Area, and Cost (PPAC) that dimensional scaling has brought over the past several decades are slowing down. To o set the slowdown in 2D scaling and continue the trajectory of PPAC improvements, coordinated innovations are needed across the system, circuit, and device abstraction levels. 3D integration may offer complementary gains to transistor density scaling. Meanwhile, 3D expands the design space of SoC adding considerations like partitioning, power delivery, signaling, and thermal management. This dissertation studies these considerations in detail. The work spans thermal analysis of a 3D CPU, system-level design space exploration of 3D ML accelerators, circuit design of a 3D-Split SRAM macro, and novel use of device-level 3D construct of Buried Power Rail (BPR) for SRAM signaling to enable next-generation computing systems in advanced CMOS. Item800V, 100A modular heatsink-less solid state circuit breaker(2022-11-27) Choudhary, Rahul, M.S. in Engineering; Huang, Alex Q.; Santoso, SuryaThis thesis presents a modular, heatsink-less, silicon-based solid-state circuit breaker for 100A and scalable in voltage. Each module is implemented on a metal core printed circuit board (MCPCB) and can sustain 150V and 100A. The presented breaker is compared with compared to SiC-based breakers on the cost and weight front for 800V and 100A. Electrical stimulation of the power module and 800V,100A application is presented. Thermal simulation of the module is done on Fusion 360. Experimental characterization and validation of the module are provided. Lastly, a comparison of the proposed breaker and SiC breaker is provided on cost front. ItemA 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC(2016-05-19) Gulati, Paridhi; Sun, Nan; Orshansky, MichaelA pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the design of a 10 bit pipelined ADC with a conventional SAR ADC as stage one. The first stage also has an integrated comparator and amplifier. A dynamic automatic gain control scheme is used for the amplification of the first stage residue voltage. Techniques such as redundancy help in achieving higher speed while bidirectional single side switching helps in reducing power consumption. The second stage is a 3 bit per cycle SAR ADC that makes use of a scaled down version of the voltage supply. The ADC designed in this project makes use of 0.13um CMOS technology and is able to achieve a sampling rate of 10MS/s and ENOB of 9.95. ItemA case study of lean software practices in an IT application support department(2011-12) Ren, Xiaofei, M.S. in Engineering; Perry, Dewayne E.; Krasner, HerbThe concept of lean manufacturing was formed at Toyota by Taiichi Ohno, who originated the system of “Just-in-Time” production with the goals of delivering high value and cutting down waste. These concepts were partially adapted to software development in an Agile development context  where the goal is to deliver value to the customers more quickly by eliminating waste and improving quality. However, we are not aware of any published attempt to adapt lean principles to IT maintenance work. The purpose of the case study reported here is to demonstrate that the principles of lean software development could be effectively applied to a specific IT application support department. It is an empirical study of lean practices in the maintenance department of a large organization. A comparison was made from the collected data from our release management tool before and after applying the lean principles to our IT group. Our analysis shows that the lean principles improved the developers’ focus on the given corrective or preventive task. Application quality also improved to a significant extent. More importantly, our customers did see more efficient support efforts that delivered good quality in a shorter time. All in all, the newly conceived support process adapting lean principles to our situation did, in fact, deliver more highly valued software to our customers more quickly while cutting down waste. On the other hand, we also learned that there were some challenges that arose from a conflict between the new lean practices and our previous practices. The most significant of these conflicts was revealed in developer work load imbalances and customer confusion due to having to communicate with different IT support teams for different type of maintenance requests. A future adjustment of how the lean principles can be applied to IT maintenance may be necessary.