Fault clearance in distributed power architectures with limited energy flow through power electronic interfaces

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Fault clearance in distributed power architectures with limited energy flow through power electronic interfaces

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Title: Fault clearance in distributed power architectures with limited energy flow through power electronic interfaces
Author: Dahlberg, Greg John
Abstract: The objective of this thesis is to determine a method for computing the amount of capacitance in a power electronic converter required to melt a fuse in the event of a line to ground fault. DC micro-grids rely on power electronic converters to change voltage levels. All converters rely on semiconductor switches that must be protected from surges of fault current. This limits the power that a converter can supply to a fuse. In many cases, sufficient power may be achieved by appropriately sizing the converters’ output capacitor.
Department: Electrical and Computer Engineering
Subject: Fault clearance DC micro-grids Limited power flow Output capacitor
URI: http://hdl.handle.net/2152/ETD-UT-2012-05-5550
Date: 2012-05

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