A BIST circuit for random jitter measurement


A BIST circuit for random jitter measurement

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Title: A BIST circuit for random jitter measurement
Author: Lee, Jae Wook
Abstract: Jitter is a dominant factor contributing to a high bit error rate (BER) in high speed I/O circuitry, and it aggravates the quality of a clock signal from a phase-locked loop (PLL), subsequently impacting a given timing budget. The recent proliferation of systems-on-a-chip (SoCs) with help of technology scaling makes jitter measurement more challenging as the SoCs integrate more I/O circuitry and PLLs within a chip. Jitter has been, however, one of the most difficult parameters to measure accurately when validating the high speed serial I/O circuitry or PLLs, mostly due to its small value. External instruments with full-fledged high precision measurement hardware, along with comprehensive analysis tools, have been used for jitter measurement, but increased test cost from long test time, signal integrity, and human intervention prevent this approach from being used for high volume manufacturing testing. Built-in self-test (BIST) solutions have recently become attractive to overcome these drawbacks, but complicated analog circuit designs that are sensitive to ever increasing process variations, and associated complex analysis methods impede their adoption in the SoCs. This dissertation studies practical random jitter measurement methods that achieve measurement accuracy by exploiting a differential approach and make the proposed methods tester-friendly solutions for an automatic test equipment (ATE). We first propose a method of measuring the average value of the random jitter, rather than measuring the jitter at every clock cycle, that can be converted to the root-mean-square (RMS) value of the random jitter, which is the key indicator of the quantity of the random jitter. Then, we propose a simple but accurate delay measurement method which uses the proposed jitter measurement method for random jitter measurement when a reference signal, such as a golden PLL output in high speed I/O validation, is not available. The validity of the proposed random jitter measurement method is supported by measurement results from a test chip. The impact of substrate noise on the signal of interest is also shown with measurements using a test chip. To address the random jitter of a clock signal when the clock is operating in its functional mode, we demonstrate a novel method for random jitter measurement that explores the shmoo capability of a low-cost production tester without relying on any BIST circuitry.
Department: Electrical and Computer Engineering
Subject: Random jitter Measurement BIST
URI: http://hdl.handle.net/2152/ETD-UT-2012-05-5513
Date: 2012-05

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