A microprocessor performance and reliability simulation framework using the speculative functional-first methodology

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A microprocessor performance and reliability simulation framework using the speculative functional-first methodology

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Title: A microprocessor performance and reliability simulation framework using the speculative functional-first methodology
Author: Yuan, Yi
Abstract: With the high complexity of modern day microprocessors and the slow speed of cycle-accurate simulations, architects are often unable to adequately evaluate their designs during the architectural exploration phases of chip design. This thesis presents the design and implementation of the timing partition of the cycle-accurate, microarchitecture-level SFFSim-Bear simulator. SFFSim-Bear is an implementation of the speculative functional-first (SFF) methodology, and utilizes a hybrid software-FPGA platform to accelerate simulation throughput. The timing partition, implemented in FPGA, features throughput-oriented, latency-tolerant designs to cope with the challenges of the hybrid platform. Furthermore, a fault injection framework is added to this implementation that allows designers to study the reliability aspects of their processors. The result is a simulator that is fast, accurate, flexible, and extensible.
Department: Electrical and Computer Engineering
Subject: Computer architecture Microarchitecture-level simulator Microprocessor simulation Multicore simulation FPGA acceleration Hardware-software co-design Speculative functional-first Timing model F-T divergence Fault injection Microprocessor reliability
URI: http://hdl.handle.net/2152/ETD-UT-2011-12-4848
Date: 2011-12

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