A bandwidth-enhanced fractional-N PLL through reference multiplication

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A bandwidth-enhanced fractional-N PLL through reference multiplication

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Title: A bandwidth-enhanced fractional-N PLL through reference multiplication
Author: Pu, Xiao
Abstract: The loop bandwidth of a fractional-N PLL is a desirable parameter for many applications. A wide bandwidth allows a significant attenuation of phase noise arising from the VCO. A good VCO typically requires a high Q LC oscillator. It is difficult to build an on-chip inductor with a high Q factor. In addition, a good VCO also requires a lot of power. Both these design challenges are relaxed with a wide loop bandwidth PLL. However a wide loop bandwidth reduces the effective oversampling ratio (OSR) between the update rate and loop bandwidth and makes quantization noise from the ΔΣ modulator a much bigger noise contributor. A wide band loop also makes the noise and linearity performance of the phase detector more significant. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this dissertation we present a new PLL architecture for bandwidth extension or phase noise reduction. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single cycle of a sinusoidal reference and used for phase updates, effectively forming a reference frequency multiplier. A higher update rate enables a higher OSR which allows for better quantization noise shaping and makes a wideband fractional-N PLL possible. However since the proposed reference multiplier utilizes the magnitude information from a sinusoidal reference to obtain phases, the derived new edges tend to cluster around the zero-crossings and form an irregular clock. This presents a challenge in lock acquisition. We have demonstrated for the first time that an irregular clock can be used to lock a PLL. The irregularity of the reference clock is taken into account in the divider by adding a cyclic divide pattern along with the ΔΣ control bits, this forces the loop to locally match the incoming patterns and achieve lock. Theoretically this new architecture allows for a 6x increase in loop BW or a 24dB improvement in phase noise. One potential issue associated with the proposed approach is the degraded spurious performance due to PVT variations, which lead to unintended mismatches between the irregular period and the divider pattern. A calibration scheme was invented to overcome this issue. In simulation, the calibration scheme was shown to lower the spurs down to inherent spurs level, of which the total energy is much less than the integrated phase noise. A test chip for proof of concept is presented and measurements are carefully analyzed.
Department: Electrical and Computer Engineering
Subject: PLL Fractional-N Bandwidth Spur
URI: http://hdl.handle.net/2152/ETD-UT-2011-08-4149
Date: 2011-08

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