Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier

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Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier

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Title: Low-power fused FFT butterfly arithmetic unit with merged multiple-constant multiplier
Author: Min, Jae Hong
Abstract: Fused floating-point arithmetic units such as a floating-point fused Dot-Product (fused DP) and a floating-point fused Add-Subtract (fused AS) are employed for the implementation of the butterfly unit of the FFT due to their characteristics of low power and less area. In addition, the fused DP has less delay and lower error. Among the elements of the fused DP, two internal mantissa multipliers occupy the largest area and consume the largest power. A Multiple-Constant Multiplier (MCM) architecture has high speed, low power consumption, and small area compared to a conventional multiplier. The MCM is used for the internal mantissa multiplier, providing a solution for low power and high performance. Despite the benefits of the MCM, it lacks precision compared to a conventional multiplier. Due to this, the butterfly unit using the MCM has higher error. In this report, a new architecture of the butterfly unit has been designed by merging conventional MCMs. The new architecture provides two options. It either reduces the error or it lowers the power compared to a conventional MCM butterfly unit.
Department: Electrical and Computer Engineering
Subject: Fused floating-point arithmetic unit Multiple-constant multiplier Butterfly unit of FFT
URI: http://hdl.handle.net/2152/ETD-UT-2010-12-2495
Date: 2010-12

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