Process variation aware low power buffer design
| Title: | Process variation aware low power buffer design |
| Author: | Lok, Mario Chichun |
| Abstract: | In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield. |
| Subject: |
Low power design
Adaptive circuit Statistical sizing Tunable circuit Adaptable optimization |
| URI: | http://hdl.handle.net/2152/ETD-UT-2010-05-1167 |
| Date: | 2010-05 |
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