Low-power techniques for high-performance pipelined analog to digital converter

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Low-power techniques for high-performance pipelined analog to digital converter

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Title: Low-power techniques for high-performance pipelined analog to digital converter
Author: Lee, Byung-geun, 1973-
Abstract: Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics. In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable-gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small. The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.18¹m CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, [power/2[superscript ENOB].Fs], is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.
Department: Electrical and Computer Engineering
Subject: Pipelined ADCs--Design and construction Operational amplifiers
URI: http://hdl.handle.net/2152/3731
Date: 2007

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