Nanometer VLSI placement and optimization for multi-objective design closure

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Nanometer VLSI placement and optimization for multi-objective design closure

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dc.contributor.advisor Pan, David Z.
dc.creator Luo, Tao, Ph. D.
dc.date.accessioned 2008-08-29T00:03:44Z
dc.date.available 2008-08-29T00:03:44Z
dc.date.created 2007-12
dc.date.issued 2008-08-29T00:03:44Z
dc.identifier.uri http://hdl.handle.net/2152/3688
dc.description.abstract Not available
dc.format.medium electronic
dc.language.iso eng
dc.rights Copyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.
dc.subject.lcsh Integrated circuits--Very large scale integration--Design and construction
dc.subject.lcsh Algorithms
dc.title Nanometer VLSI placement and optimization for multi-objective design closure
dc.description.department Electrical and Computer Engineering
dc.identifier.oclc 212376769
dc.identifier.recnum b69724027
dc.type.genre Thesis
dc.type.material text
thesis.degree.department Electrical and Computer Engineering
thesis.degree.discipline Electrical and Computer Engineering
thesis.degree.grantor The University of Texas at Austin
thesis.degree.level Doctoral
thesis.degree.name Doctor of Philosophy

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