Design and evaluation of a technology-scalable architecture for instruction-level parallelism

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Design and evaluation of a technology-scalable architecture for instruction-level parallelism

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Title: Design and evaluation of a technology-scalable architecture for instruction-level parallelism
Author: Nagarajan, Ramadass, 1977-
Abstract: Not available
Department: Computer Sciences
Subject: Computer architecture--Design Computer architecture--Evaluation High performance processors--Design and construction High performance processors--Evaluation Parallel processing (Electronic computers) Threads (Computer programs)
URI: http://hdl.handle.net/2152/3534
Date: 2007

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