Addressing the memory bottleneck in packet processing systems

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Addressing the memory bottleneck in packet processing systems

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dc.contributor.advisor Vin, Harrick M.
dc.creator Mudigonda, Jayaram
dc.date.accessioned 2008-08-28T22:42:23Z
dc.date.available 2008-08-28T22:42:23Z
dc.date.created 2005
dc.date.issued 2008-08-28T22:42:23Z
dc.identifier.uri http://hdl.handle.net/2152/2307
dc.description.abstract Not available
dc.format.medium electronic
dc.language.iso eng
dc.rights Copyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.
dc.subject.lcsh Packet switching (Data transmission)
dc.subject.lcsh Computer network protocols
dc.title Addressing the memory bottleneck in packet processing systems
dc.description.department Computer Sciences
dc.identifier.oclc 71004382
dc.identifier.recnum b61126135
dc.type.genre Thesis
dc.type.material text
thesis.degree.department Computer Sciences
thesis.degree.discipline Computer Sciences
thesis.degree.grantor The University of Texas at Austin
thesis.degree.level Doctoral
thesis.degree.name Doctor of Philosophy

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