I/O test methods in high-speed wireline communication systems

Repository

I/O test methods in high-speed wireline communication systems

Show simple record

dc.contributor.advisor Abraham, Jacob A.
dc.creator Dou, Qingqi
dc.date.accessioned 2012-10-12T19:01:16Z
dc.date.available 2012-10-12T19:01:16Z
dc.date.created 2008-08
dc.date.issued 2012-10-12
dc.identifier.uri http://hdl.handle.net/2152/18345
dc.description.abstract The advent of serial tera-bit telecommunication and multi-gigahertz I/O interfaces is posing challenges on the semiconductor and ATE industries. There is a gap in signal integrity testing between what has been specified in serial link standards and what can be practically tested in production. A thorough characterization and a more cost-effective test of the signal integrity, such as BER, jitter, and eye margin, are critical to identify and isolate the root cause of the system degradation and to the binning in production. In this dissertation, measurement and testing schemes on signal integrity are explored. A solution for diagnosing jitter and predicting the range of consequent BER is proposed. This solution is applicable to decomposition of correlated and uncorrelated jitter in both clock and data signals. The statistical information of jitter is estimated using TLC functions. TLC treats jitter in its original form, as a time series, resulting in good accuracy in the decomposition. Hardware results in a PLL indicate that the approach is still valid when the traditional histogram-based method fails. This approach can be implemented using only one-shot capture instead of multiple captures to average out the uncorrelated jitter from the correlated jitter. Therefore, the TLC functions enable test time reduction in jitter decomposition compared to traditional averaging methods. Hardware measurements on stressed data signals are presented to validate the proposed technique. We have also explored low cost, high bandwidth techniques using Built In Self Test(BIST) for on-chip jitter measurement. Undersampling provides a lowcost test solution for on-chip jitter measurement. However, it suffers from sampling clock phase error and time quantization noise. These timing uncertainties on the test accuracy of the traditional technique using a single channel structure can be alleviated by extracting the correlation between two channels using a single reference clock. Simulation results indicate that the proposed approach can achieve a better measurement accuracy and a higher degree of tolerance to sampling clock uncertainty and quantization error than does the single-channel structure, with little additional test overhead. TIADCs provide an attractive solution to the realization of analog front ends in high speed communication systems,such as 10GBASE-T and 10GBASEFiber. However, gain mismatch, offset mismatch, and sampling time mismatch between time-interleaved channels limit the performance of TIADCs. A low-cost test scheme is developed to measure timing mismatch using an undersampling clock. This method is applicable to an arbitrary number of channels, achieving picosecond resolution with low power consumption. Simulation results and hardware measurements on a 10GSps TIADC are presented to validate the proposed technique.
dc.format.medium electronic
dc.language.iso eng
dc.rights Copyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.
dc.subject.lcsh Wireless communication systems
dc.subject.lcsh Signal processing--Digital techniques
dc.title I/O test methods in high-speed wireline communication systems
dc.description.department Electrical and Computer Engineering
dc.type.genre Thesis
dc.type.material text
thesis.degree.department Electrical and Computer Engineering
thesis.degree.discipline Electrical and Computer Engineering
thesis.degree.grantor The University of Texas at Austin
thesis.degree.level Doctoral
thesis.degree.name Doctor of Philosophy

Files in this work

Download File: douq33990.pdf
Size: 2.341Mb
Format: application/pdf

This work appears in the following Collection(s)

Show simple record


Advanced Search

Browse

My Account

Statistics

Information