| Title: | High level static analysis of system descriptions for taming verification complexity |
| Author: | Vasudevan, Shobha |
| Abstract: | Not available |
| Department: | Electrical and Computer Engineering |
| Subject: |
Computer systems
Computer systems--Verification Formal methods (Computer science) Computer algorithms |
| URI: | http://hdl.handle.net/2152/15978 |
| Date: | 2007-12 |