Gate current modeling through high-k materials and compact modeling of gate capacitance

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dc.contributor.advisor	Banerjee, Sanjay
dc.contributor.advisor	Tasch, Al F.
dc.creator	Mudanai, Sivakumar Panneerselvam
dc.date.accessioned	2011-03-28T21:59:22Z
dc.date.available	2011-03-28T21:59:22Z
dc.date.created	2001-08
dc.date.issued	2011-03-28
dc.identifier.uri	http://hdl.handle.net/2152/10757
dc.description.abstract	Not available
dc.format.medium	electronic
dc.language.iso	eng
dc.rights	Copyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.
dc.subject	Computer engineering
dc.subject	Dielectric devices
dc.title	Gate current modeling through high-k materials and compact modeling of gate capacitance
dc.rights.holder	Restricted
dc.description.department	Electrical and Computer Engineering
dc.type.genre	Thesis
dc.type.material	text
thesis.degree.department	Electrical and Computer Engineering
thesis.degree.discipline	Electrical and Computer Engineering
thesis.degree.grantor	The University of Texas at Austin
thesis.degree.level	Doctoral
thesis.degree.name	Doctor of Philosophy